Title :
Test length reduction for accumulator-based self-test
Author :
Mayer, Frank ; Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
Many circuits contain adders and subtracters that can be configured as accumulators. When the circuits are tested, these accumulators may operate as test pattern generators. However, often long pattern sequences are required to achieve high fault coverage. This paper shows that an optimal selection of the initial state and the input value of the accumulators can significantly reduce test lengths. An efficient method to perform this optimization is presented
Keywords :
adders; automatic testing; built-in self test; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; BIST; accumulator-based self-test; adders; fault coverage; initial state; input value; subtracters; test length reduction; test pattern generators; Adders; Automatic testing; Built-in self-test; Circuit testing; Clocks; Compaction; Degradation; Hardware; Polynomials; Registers;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.612883
