A comprehensive trapped charge profiling technique for SONOS flash EEPROMs

Author

Nair, Pradeep R. ; Kumar, P. Bharath ; Sharma, Ravinder ; Mahapatra, S. ; Kamohara, S.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

403

Lastpage

406

Abstract

Trapped charge profiles under CHE program of SONOS flash cells are uniquely determined and verified using I-V, GIDL and CP measurements and Monte Carlo simulations. The prospect of profiling using I-V measurement alone is discussed. The inaccuracy associated with conventional CP technique is discussed. The correct method of CP simulation for programmed SONOS devices is shown and programming induced interface-trap generation is estimated.

Keywords

Monte Carlo methods; circuit simulation; flash memories; integrated circuit measurement; interface states; semiconductor-insulator-semiconductor structures; CP measurements; GIDL measurement; I-V measurement; Monte Carlo simulations; SONOS flash cells; flash EEPROMs; interface-trap generation; programmed SONOS devices; trapped charge profiling; Channel hot electron injection; Charge measurement; Current measurement; Degradation; EPROM; Electric variables measurement; Electron traps; Electronic mail; Pulse measurements; SONOS devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419170

Filename

1419170

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3000963