Power optimization of future transistors and a resulting global comparison standard

We report a global power minimization methodology for future transistors and use it as a comparison standard to quantify the relative and absolute impact of material and structural innovations on power and speed. In addition, we put the relative tradeoffs of device design in perspective of global metrics. In the process, we also develop and verify two key enabling models: (1) to calculate inverter delay and (2) to estimate gate leakage. Although applicable to any futuristic technology node, we specifically target 45nm high-performance node with an 18nm gate length double gate FET.