Implementation and Analysis of Power Consumption for a Power Optimized Decimator Designed for Cascaded Sigma-Delta A/D Converters

This paper presents the implementation and power analysis of an efficient decimator architecture for cascaded sigma-delta (SigmaDelta) modulators. The recombination logic for cascaded modulators in general and a gain error correction for continuous time (CT) modulators are integrated into the first decimation stage. An appropriate filter topology is derived and synthesized in a 0.18 mum CMOS technology using synopsys design compiler. The power consumption of the various blocks is analyzed using stimuli of a SOFO SigmaDelta-modulator and synopsys primepower. A comparison of the proposed architecture to a conventional implementation shows a remarkable reduction of power consumption by a factor of 4.