New low-cost thermally stable process to reduce silicon substrate: a way to extreme frequencies for high volume Si technologies

Author

Detcheverry, C. ; van Noort, W.D. ; Havens, R.J.

Author_Institution

Philips Res. Labs., Leuven, Belgium

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

463

Lastpage

466

Abstract

Using a semi-insulating channel stopper (SICS) layer, silicon substrate RF losses have been eliminated on high resistive silicon wafers (HRS) up to 100 GHz, even after thermal treatments up to 1100°C. The integration of the SICS layer is demonstrated at the bottom of shallow trench isolation (STI) in a state-of-the-art CMOS technology. These results open a way to easily integrate low-cost high quality passive devices into standard high volume Si technologies.

Keywords

CMOS integrated circuits; elemental semiconductors; losses; millimetre wave integrated circuits; RF losses; high quality passive devices; high resistive silicon wafers; high volume Si technology; low-cost thermally stable process; semi-insulating channel stopper layer; shallow trench isolation; silicon substrate reduction; state-of-the-art CMOS technology; thermal treatments; CMOS technology; Conductivity; Coplanar waveguides; Fabrication; Isolation technology; Laboratories; Microwave technology; Radio frequency; Silicon carbide; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419188

Filename

1419188