VLSI architectural synthesis for an acoustic echo cancellation application

Author

Sentieys, Olivier ; Martin, Eric ; Philippe, Jean-Luc

Author_Institution

LASTI-ENSSAT, Rennes Univ., Lannion, France

fYear

1993

fDate

20-22 Oct 1993

Firstpage

84

Lastpage

92

Abstract

An architectural synthesis tool dedicated to Digital Signal Processing, GAUT, is presented. Synthesis is achieved under both real time and silicon cost constraints. The algorithm is first described using a high level behavioral language. The control and data flow graph (CDFG) obtained is synthesized into processing control, memorization and communication units. These specifications are in VHDL, thus enabling the interconnection with CAD and simulation tools. An application of acoustic echo cancellation was synthesized, and it is show that the method may also be used to evaluate the complexity of various signal processing algorithms that satisfy the application constraints

Keywords

VLSI; acoustic signal processing; adaptive filters; circuit layout CAD; data flow graphs; digital filters; digital signal processing chips; echo suppression; hardware description languages; high level synthesis; parallel algorithms; parallel architectures; parallel languages; CAD tool; DSP; GAUT tool; VHDL; VLSI architectural synthesis; acoustic echo cancellation application; adaptive filtering algorithms; application constraints; complexity; control and data flow graph; high level behavioral language; pipeline architecture; signal processing algorithms; silicon cost constraints; transversal filter; Communication system control; Costs; Digital signal processing; Echo cancellers; Flow graphs; Process control; Signal processing algorithms; Signal synthesis; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, VI, 1993., [Workshop on]

Conference_Location

Veldhoven

Print_ISBN

0-7803-0996-0

Type

conf

DOI

10.1109/VLSISP.1993.404499

Filename

404499