The effects of annealing ambients on dielectric strength of gate oxides with tungsten polycide gate

Author

Tanigaki, Yukio ; Moribe, Shunji ; Itagaki, T.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1988

fDate

13-14 June 1988

Firstpage

191

Lastpage

197

Abstract

The effects of annealing ambients (Ar, N/sub 2/, and O/sub 2/) on the dielectric strength of silicon dioxide with a CVD WSi/sub 2/ polycide gate were investigated. The degradation of the dielectric strength of the gate oxide and Si precipitation at the edge of the WSi/sub 2/ polycide gate were observed only for devices annealed in Ar ambient. The dielectric strength of the gate oxide decreased with higher annealing temperature, longer annealing time, and larger composition ration (Si/W) of the WSi/sub 2/ film. A mechanism for the effects is proposed.<>

Keywords

annealing; dielectric thin films; electric strength; metallisation; oxidation; silicon compounds; tungsten compounds; (Ar; CVD; N/sub 2/; O/sub 2/; SiO/sub 2/-WSi/sub 2/; annealing ambients; annealing temperature; annealing time; dielectric strength; gate oxides; polycide gate; precipitation; Annealing; Argon; Breakdown voltage; Dielectric breakdown; Electric breakdown; Plasma measurements; Plasma temperature; Silicon compounds; Tungsten; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE

Conference_Location

Santa Clara, CA, USA

Type

conf

DOI

10.1109/VMIC.1988.14192

Filename

14192