• DocumentCode
    3001688
  • Title

    Energy-aware Scheduling: Models and Complexity Results

  • Author

    Aupy, Guillaume

  • Author_Institution
    LIP, Ecole Normale Super. de Lyon, Lyon, France
  • fYear
    2012
  • fDate
    21-25 May 2012
  • Firstpage
    2478
  • Lastpage
    2481
  • Abstract
    This paper presents several energy-aware scheduling algorithms whose design is optimized for different speed models. Dynamic Voltage and Frequency Scaling (DVFS) is a model frequently used to reduce the energy consumption of a schedule, but it has negative effect on reliability. While the reliability of a schedule can sometimes be neglected (battery powered systems such as cell-phones or personal computers), it becomes extremely important when considering massively parallel architectures (petascale, exascale). In this work, we consider the problem of minimizing the energy within a make span constraint. Additionally, we consider two models, one that takes into account a reliability constraint, and one that does not. We assume that the mapping is given, say by an ordered list of tasks to execute on each processor, and we aim at optimizing the energy consumption while enforcing a prescribed bound on the execution time. While it is not possible to change the allocation of a task, it is possible to change its speed. Rather than using a local approach such as backfilling, we consider the problem as a whole and study the impact of several speed variation models on its complexity. To improve the reliability of a schedule while reducing the energy consumption, we allow for the re-execution of some tasks. We present several results in that framework, as well as future research plans.
  • Keywords
    energy consumption; parallel architectures; power aware computing; processor scheduling; DVFS; backfilling; battery powered system; dynamic voltage and frequency scaling; energy consumption; energy minimization; energy-aware scheduling algorithm; exascale; execution time; make span constraint; parallel architecture; petascale; processor; reliability constraint; schedule reliability; speed model; task allocation; task reexecution; Computational modeling; Energy consumption; Polynomials; Processor scheduling; Reliability theory; Schedules;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4673-0974-5
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2012.307
  • Filename
    6270873