DocumentCode
3001692
Title
The use of selective silicide plugs for submicron contact fill
Author
Wei, Chih-Shih ; Murali, Venkatesan ; Dass, M. Lawrence A ; Fraser, David B. ; Borland, John
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
1989
fDate
12-13 Jun 1989
Firstpage
136
Lastpage
143
Abstract
A novel contact fill scheme using a silicide plug has been developed. The scheme combines selective epitaxial Si growth (SEG) and silicide formation to form selective silicide contact plugs. Silicide plugs can be implemented in both n+ and p+ contacts with low contact resistance, high temperature stability, and good planarity. TEM and electrical measurements show that the above approach can be used to fill contact depth up to 1 μm and contact aspect ratio up to 1. The lack of a silicidation stop and the incomplete epi-Si consumption are two issues to be solved. For deeper contacts or contacts with higher aspect ratio, postsilicidation plug implantations become necessary to guarantee low contact resistances
Keywords
CMOS integrated circuits; contact resistance; integrated circuit technology; metallisation; vapour phase epitaxial growth; CMOS; TEM; contact aspect ratio; contact depth; contact resistance; electrical measurements; high temperature stability; planarity; postsilicidation plug implantations; selective epitaxial Si growth; selective silicide plugs; submicron contact fill; Contact resistance; Etching; Hydrogen; Planarization; Plugs; Semiconductor films; Silicides; Silicon; Stability; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE
Conference_Location
Santa Clara, CA
Type
conf
DOI
10.1109/VMIC.1989.78016
Filename
78016
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