Title :
An object oriented programming approach for the generation of test vectors for VLSI design
Author_Institution :
EDP Coll., Hato Rey, Puerto Rico
Abstract :
A new approach was used in the development of the implementation of a minimal test vector generation algorithm for single and multiple fault detection in a PLA. The conversion of product terms from binary notation to decimal notation simplifies the development of the C language subroutines used for the implementation. The ordered position in our approach allows us to find a complete test vector in a single comparison in some instances and makes it feasible to find complete test vectors having a dH=k in an n-dimensional subspace, e.g., even if 99.21875% of the minterms in an 8-dimensional subspace are bounded
Keywords :
VLSI; circuit CAD; integrated circuit design; integrated circuit testing; object-oriented programming; programmable logic arrays; C language subroutine; PLA; VLSI design; decimal notation; minimal test vector generation algorithm; multiple fault detection; n-dimensional subspace; object oriented programming; single fault detection; Algorithms; Circuit faults; Fault detection; Hamming distance; Lead compounds; Manufacturing processes; Object oriented programming; Programmable logic arrays; Testing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.612888