High-level design synthesis with redundancy removal for high speed testable adders

Author

Wagh, Mahesh ; Chen, Chien-In Henry

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

Volume

6

fYear

1999

fDate

36342

Firstpage

358

Abstract

Current synthesis tools are capable of handling area and timing constraints. Synthesis for testability process ensures that the design is testable. In this paper CAD tools capable of handling the testability requirements are explained and emphasis is on redundancy removal for designing high speed testable binary adders. The 1.2 μm CMOS realization of the 32-bit testable adder performs the addition operation in 4.09 ns. Removal of redundant logic yields a 100% testable design with significant improvement in performance characteristics. A 15% improvement in speed and a 25% reduction in overall area has been observed when compared with the untestable design

Keywords

CMOS logic circuits; adders; design for testability; high level synthesis; high-speed integrated circuits; redundancy; timing; 1.2 micron; 32 bit; 4.09 s; CMOS realization; addition operation; area constraints; high speed testable adders; high-level design synthesis; performance characteristics; redundancy removal; redundant logic; testability process; timing constraints; Adders; Circuit faults; Circuit synthesis; Circuit testing; Design automation; Design optimization; Logic design; Logic testing; Pipelines; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780169

Filename

780169