DocumentCode
3002354
Title
MIS-MV: optimization of multi-level logic with multiple-values inputs
Author
Lavagno, L. ; Malik, S. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
560
Lastpage
563
Abstract
Techniques are presented for the optimization of multi-level logic with multiple-valued input variables. The motivation for this is to tackle the input encoding problem in logic synthesis, where binary codes need to be found for the different values of a symbolic input variable. Multi-level multiple-valued optimization is used to generate constraints that are used to determine the codes. The state assignment problem in sequential logic synthesis can be approximated as an input encoding problem by ignoring the next state field, which is reasonable when the primary output logic, dominates the next state logic. A novel technique is presented for extracting common factors with multiple-valued variables, and it is shown how other multi-level optimization techniques are easily extended with multiple-valued variables. These ideas have been implemented as algorithms in the MIS-MV program. Practical issues are also presented regarding implementation. Experimental results are also given.<>
Keywords
logic CAD; many-valued logics; MIS-MV; common factors; logic synthesis; multi-level logic; multi-level optimization; multiple-values inputs; sequential logic synthesis; state assignment problem; Automatic logic units; Binary codes; Circuit synthesis; Constraint optimization; Contracts; Digital circuits; Encoding; Input variables; Logic circuits; Minimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129981
Filename
129981
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