What will end CMOS scaling - money or physics? [Panel Discussion Topics]

Summary form only given. CMOS scaling limits have been projected and then been defeated several times. Many of the theoretical physics limits turn out to be materials or process limits, and have been addressed with ever more capital intensive manufacturing equipment and development efforts. However, the success of Moore\´s law is based on achieving, "smaller, cheaper, faster" all at the same time and it is clear that this is extremely challenging going forward. Lithography costs per level are increasing as fast as dimensions are shrinking. Sub-wavelength patterning, while physically possible, is so costly that only the highest volume applications can take advantage of it. The cost reduction from 300mm wafers is offset by increased development costs for device and equipment manufacturers alike. Transistors leakage has increased by several orders of magnitude, adding extra cost for the design of complex power management circuitry. Interconnect delays should have been mitigated with low-k dielectrics and copper, but no "cure" has been found for the porosity challenge and resistivity is growing exponentially in small wires and contacts. Is the cost-to-scale exceeding Moore\´s law potential benefit? To debate this topic we have invited a distinguished panel from industry leaders who face the challenges of budgets and physics everyday. They come from around the world and represent a cross section of IDM, foundry and academic perspectives.