DocumentCode
3002647
Title
QSYN: Queueing networks synthesis for system on chip
Author
Hammami, O.
fYear
2008
fDate
20-22 Dec. 2008
Firstpage
22
Lastpage
27
Abstract
Queueing networks represent a powerful model of computation (MOC) with strong theoretical foundations and a wide range of applications. Design productivity for system on chip (SOC) requires increasing the level of abstraction for the design of SOC. However, achieving better productivity through raising the level of abstraction can only be obtained with the help of automatic MOC transformation techniques. In this paper, we propose QSYN a tool for the automatic transformation of queueing network based MOC to an executable platform on FPGA. Case studies demonstrate the validity of our approach.
Keywords
field programmable gate arrays; queueing theory; system-on-chip; FPGA; SOC; automatic transformation techniques; queueing networks synthesis; system on chip; Computational modeling; Computer networks; Field programmable gate arrays; Multiprocessing systems; Network servers; Network synthesis; Performance analysis; Productivity; Queueing analysis; System-on-a-chip; FPGA; MOC; Queueing network; SOC;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Test Workshop, 2008. IDT 2008. 3rd International
Conference_Location
Monastir
Print_ISBN
978-1-4244-3479-4
Electronic_ISBN
978-1-4244-3478-7
Type
conf
DOI
10.1109/IDT.2008.4802458
Filename
4802458
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