The research on CPU nuclear model in SoC 1000C based on automatic gating clock technology

This paper first introduces automatic gating technology and its application on the CPU nucleus of Soc 1000 C. This paper puts forward a clock network design scheme that can exactly and credibly analyzes the sequence. It can reduce the SoC clock power dissipation without adding physical design complexity and also can improve the sequence capability and the CMOS chip unilateralist. At the end of this paper an experiment is given, the results of which illustrate that to qsort program the new method can reduce 35% power dissipation compared to traditional method and to Dijkstra program the new method can reduce 46% power dissipation compared to traditional method.