DocumentCode :
3002890
Title :
The research on CPU nuclear model in SoC 1000C based on automatic gating clock technology
Author :
Li, Tao ; Wang, Yilei ; Tian, Shengwen ; Lu, Lan
Author_Institution :
Network Center, Lu Dong Univ., Yantai
fYear :
2008
fDate :
1-3 Sept. 2008
Firstpage :
2747
Lastpage :
2750
Abstract :
This paper first introduces automatic gating technology and its application on the CPU nucleus of Soc 1000 C. This paper puts forward a clock network design scheme that can exactly and credibly analyzes the sequence. It can reduce the SoC clock power dissipation without adding physical design complexity and also can improve the sequence capability and the CMOS chip unilateralist. At the end of this paper an experiment is given, the results of which illustrate that to qsort program the new method can reduce 35% power dissipation compared to traditional method and to Dijkstra program the new method can reduce 46% power dissipation compared to traditional method.
Keywords :
CMOS integrated circuits; system-on-chip; CPU nuclear model; SoC; automatic gating clock technology; clock network design scheme; clock power dissipation; Automatic control; CMOS logic circuits; CMOS technology; Clocks; Electronic design automation and methodology; Frequency synchronization; Paper technology; Power dissipation; Registers; Switches; CMOS; Gating Clock; SoC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Automation and Logistics, 2008. ICAL 2008. IEEE International Conference on
Conference_Location :
Qingdao
Print_ISBN :
978-1-4244-2502-0
Electronic_ISBN :
978-1-4244-2503-7
Type :
conf
DOI :
10.1109/ICAL.2008.4636640
Filename :
4636640
Link To Document :
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