Title :
Why is CMOS scaling coming to an END?
Author :
Haron, Nor Zaidi ; Hamdioui, Said
Author_Institution :
Comput. Eng. Lab., Delft Univ. of Technol., Delft
Abstract :
The continued physical feature size scaling of complementary metal oxide semiconductor (CMOS) transistors is experiencing asperities due to several factors, and it is expected to reach its boundary at size of 22 nm technology by 2018. This paper discusses and analyzes the main challenges and limitations of CMOS scaling, not only from physical and technological point of view, but also from material (e.g., high-k vs. low-k) and economical point of view as well. The paper also addresses alternative non-CMOS devices (i.e., nanodevices) that are potentially able to solve the CMOS problems and limitations.
Keywords :
CMOS integrated circuits; nanoelectronics; transistors; CMOS scaling; complementary metal oxide semiconductor transistors; constant-field scaling; nonCMOS devices; CMOS technology; Dielectric materials; Dielectric substrates; High K dielectric materials; High-K gate dielectrics; Inorganic materials; MOSFETs; Power generation economics; Semiconductor materials; Silicon; CMOS; constant-field scaling; dynamic/static power; high/low-k materials; lithography; nanodevices;
Conference_Titel :
Design and Test Workshop, 2008. IDT 2008. 3rd International
Conference_Location :
Monastir
Print_ISBN :
978-1-4244-3479-4
Electronic_ISBN :
978-1-4244-3478-7
DOI :
10.1109/IDT.2008.4802475
