High performance and low power transistors integrated in 65nm bulk CMOS technology

Author

Luo, Z. ; Steegen, A. ; Eller, M. ; Mann, R. ; Baiocco, C. ; Nguyen, P. ; Kim, L. ; Hoinkis, M. ; Ku, V. ; Klee, V. ; Jamin, F. ; Wrschka, P. ; Shafer, P. ; Lin, W. ; Fang, S. ; Ajmera, A. ; Tan, W. ; Park, D. ; Mo, R. ; Lian, J. ; Vietzke, D. ; Coppock,

Author_Institution

IBM Semicond. R&D Center

fYear

2004

fDate

2004

Firstpage

661

Lastpage

664

Abstract

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node

Keywords

CMOS integrated circuits; MOSFET; low-power electronics; 65 nm; CMOS technology; MOSFET; NiSi; advance co-implants; low power transistors; low temperature MOL process; plasma nitrided gate oxide; CMOS technology; Energy consumption; Leakage current; MOSFET circuits; Plasma devices; Plasma temperature; Power transistors; Random access memory; Space technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419254

Filename

1419254