DocumentCode
3003053
Title
A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain
Author
Blosse, A. ; Ramkumar, K. ; Gopalan, P. ; Hsu, C.T. ; Narayanan, S. ; Narasimhan, G. ; Gettle, R. ; Kapre, R. ; Sharifzadeh, Sara
Author_Institution
Cypress Semicond., San Jose, CA, USA
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
669
Lastpage
672
Abstract
A novel CMOS process architecture comprising of 1.5 nm equivalent oxide thickness (EOT) oxide/nitride (O/N) gate dielectric, self aligned shallow trench isolation (SASTI), dual poly/W gate and W cladded source/drain is shown to have low gate dielectric leakage with excellent boron blocking, no dopant cross-diffusion and lower gate and source/drain parasitic resistance.
Keywords
CMOS integrated circuits; boron; integrated circuit design; isolation technology; 1.5 nm; 65 nm; CMOS process architecture; boron blocking; dopant cross diffusion; equivalent oxide thickness; gate dielectric leakage; parasitic resistance; self aligned shallow trench isolation; Annealing; CMOS process; Costs; Dielectrics; Electrodes; Etching; Implants; Oxidation; Plasma temperature; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN
0-7803-8684-1
Type
conf
DOI
10.1109/IEDM.2004.1419256
Filename
1419256
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