Title :
Charge trapping in aggressively scaled metal gate/high-k stacks
Author :
Gusev, E.P. ; Narayanan, V. ; Zafar, S. ; Cabral, C., Jr. ; Carrier, Erin ; Bojarczuk, N. ; Callegari, A. ; Carruthers, R. ; Chudzik, M. ; Emic, C.D. ; Duch, E. ; Jamison, P. ; Kozlowski, P. ; LaTulipe, D. ; Maitra, K. ; McFeely, F.R. ; Newbury, J. ; Paru
Author_Institution :
IBM Semicond. R&D Center, IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or Tinv, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates); (ii) high-k dielectric material (HfO2, HfO2:N, HfSiO, HfSiON, ZrO2, Al2O3); (iii) high-k deposition technique (MOCVD vs. ALD); (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-k layer and poly-Si plays a major role in charge trapping degradation.
Keywords :
MOCVD; aluminium compounds; atomic layer deposition; dielectric materials; electron traps; hafnium compounds; silicon compounds; zirconium compounds; Al2O3; HfO2:N; HfSiON; MOCVD; ZrO2; annealing effects; atomic layer deposition; bottom interface; charge trapping; forming gas; fully silicided gates; gate electrode material; high-k deposition technique; high-k dielectric material; high-k stacks; metal gate stacks; poly-Si gates; Annealing; Degradation; Dielectric materials; Electrodes; Electron traps; High K dielectric materials; High-K gate dielectrics; MOCVD; Stress; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419274
