Potential of low temperature CMOS with normal and superconductive interconnect

Author

Krusius, J.P. ; Pence, W.E.

Author_Institution

Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA

fYear

1989

fDate

12-13 Jun 1989

Firstpage

233

Lastpage

240

Abstract

The potential of high-T_c superconductive interconnects in CMOS-based digital systems is examined theoretically using system simulation, a new design tool for electronic packages and systems. A 1.5-μm-technology CMOS processor, with 500000 circuits partitioned into 25 chips packaged as a single multichip module, is examined. The best implementation with superconductive interconnects at 77 K has a cycle time of 9.6 ns, which is about six times faster than the baseline design with normal metal (Al, Cu) interconnects at 300 K

Keywords

CMOS integrated circuits; VLSI; digital integrated circuits; high-temperature superconductors; hybrid integrated circuits; metallisation; 1.5 micron; 25 chips; 300 K; 77 K; 9.6 ns; Al-Cu alloy interconnects; CMOS processor; CMOS-based digital systems; VLSI; cycle time; high temperature superconductors; high-T_c superconductive interconnects; low temperature CMOS; multilevel interconnection; single multichip module; superconductive interconnect; system simulation; CMOS process; CMOS technology; Circuit simulation; Inorganic materials; Integrated circuit interconnections; Packaging; Superconducting materials; Superconductivity; Temperature; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1989.78026

Filename

78026