Title :
A 500 MHz 1-stage 32 bit ALU with self-running test circuit
Author :
Yoshida, T. ; Matsubara, G. ; Yoshioka, S. ; Tago, H. ; Suzuki, S. ; Goto, N.
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
A 500 MHz 1-stage 32 bit ALU has been designed and fabricated using 0.3 /spl mu/m CMOS process. Main features are a 1.56 ns DPL (Double path-transistor logic) adder and a compact barrel shifter using a newly developed 4-input MUX scheme. A BIST (built-in self test) circuit enables 500 MHz real-time testing. The chip size is 1 mm/spl times/0.38 mm.
Keywords :
CMOS logic circuits; VLSI; adders; built-in self test; digital arithmetic; multiplexing equipment; 0.3 micron; 1.56 ns; 32 bit; 4-input MUX scheme; 500 MHz; ALU; BIST; CMOS process; DPL adder; compact barrel shifter; double path-transistor logic; real-time testing; self-running test circuit; Adders; Automatic testing; Circuit testing; Clocks; Delay; Detectors; Page description languages; Reduced instruction set computing; Ultra large scale integration; Zinc;
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
DOI :
10.1109/VLSIC.1995.520664
