Symbolic Synthesis and Verification of Hierarchical Interface-based Supervisory Control

Hierarchical interface-based supervisory control (HISC) decomposes a discrete-event system (DES) into a high-level subsystem which communicates with n ges 1 low-level subsystems, through separate interfaces which restrict the interaction of the subsystems. It provides a set of local conditions that can be used to verify global conditions such as nonblocking and controllability. The current HISC verification and synthesis algorithms are based upon explicit state and transition listings which limit the size of a given level to about 10⁷ states when 1GB of memory is used. In this paper, we extend the HISC approach by introducing a set of predicate based fixed point operators that allow us to do a per level synthesis to construct for each level a maximally permissive supervisor that satisfies the corresponding HISC conditions. We prove that these fixpoint operators compute the required level-wise supremal languages. We then present algorithms that implement the fixpoint operators. Based on these algorithms, a symbolic implementation is briefly discussed which can be implemented using binary decision diagrams. We also discuss a method to implement our synthesized supervisors in a more compact manner. A large manufacturing system example (worst case state space on the order of 10³⁰) extended from the ALP example is briefly discussed. The example showed that we can now handle a given level with a statespace as large as 10 ¹⁵ states, using less than 160MB of memory. This represents a significant improvement in the size of systems that can be handled by the HISC approach. A software tool for synthesis and verification of HISC systems using our approach was also developed