The analysis and test of real-time performance for time-triggered CAN bus

Author

Jianxin, Liu ; Xuefeng, Guan ; Ping, Tan

Author_Institution

Sch. of Mech. Eng. & Autom., Xihua Univ., Chengdu

fYear

2008

fDate

1-3 Sept. 2008

Firstpage

3005

Lastpage

3009

Abstract

The time triggered architecture for CAN is analyzed. The implementation issue of time triggered architecture based on PIC16F913 single chip processor and CAN controller MCP2515 is designed. The mathematical model for the CAN bus delay under the worst case is given. And the real-time ability is improved by using the method of TDMA. At last, a test system is build and the result is discussed. The experiment is based on the automotive engine management, the result proves that using time triggered architecture can not only manage the message transmission but also improve the bandwidth utilization.

Keywords

controller area networks; field buses; microprocessor chips; time division multiple access; CAN bus; MCP2515; PIC16F913 single chip processor; TDMA; automotive engine management; bandwidth utilization; time division multiple access; time triggered architecture; Access protocols; Automatic testing; Automation; Decoding; Delay effects; Logistics; Mechanical engineering; Performance analysis; System testing; Time division multiple access; CAN Bus; Network performance test; Real-time system; Time-Triggered;

fLanguage

English

Publisher

ieee

Conference_Titel

Automation and Logistics, 2008. ICAL 2008. IEEE International Conference on

Conference_Location

Qingdao

Print_ISBN

978-1-4244-2502-0

Electronic_ISBN

978-1-4244-2503-7

Type

conf

DOI

10.1109/ICAL.2008.4636693

Filename

4636693