DocumentCode
3004145
Title
A 375 MHz 1 /spl mu/m CMOS 8-bit multiplier
Author
Rogenmoser, R. ; Qiuting Huang
Author_Institution
Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
fYear
1995
fDate
8-10 June 1995
Firstpage
13
Lastpage
14
Abstract
A signed 8-bit pipelined multiplier has been implemented in a standard 1.0 /spl mu/m CMOS process. It was successfully tested up to 375 MHz. This performance was achieved using the true single-phase clocking technique, fine-grain pipelining, and merging the combinational logic into the pipeline registers.
Keywords
CMOS logic circuits; clocks; combinational circuits; multiplying circuits; pipeline arithmetic; 1 micron; 375 MHz; 8 bit; CMOS; combinational logic; fine-grain pipelining; pipeline registers; signed 8-bit pipelined multiplier; true single-phase clocking technique; Adders; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Delay; Merging; Pipeline processing; Registers; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520665
Filename
520665
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