DocumentCode
3004164
Title
Depletion-free poly-Si gate high-k CMOSFETs
Author
Kim, W.S. ; Kamiyama, S. ; Aoyama, T. ; Itoh, H. ; Maeda, T. ; Kawahara, T. ; Torii, K. ; Kitajima, H. ; Arikado, T.
Author_Institution
Dept. of Res., Semicond. Leading Edge Technol., Inc., Ibaraki, Japan
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
833
Lastpage
836
Abstract
For the first time, we report poly-Si gate CMOSFETs fabricated using Hf-based stacked gate dielectrics and inverted gate implantation (IGI) that are depletion-free by virtue of the Fermi pinning effect. The sub-threshold and transconductance characteristics of surface channel IGI transistors (which include a P-doped gate for PMOS and a B-doped gate for NMOS) are enhanced because there is no gate depletion. The insertion of a thin AlOx results in some change in threshold voltage for PFETs, which demonstrated controllability of the threshold voltage by gate dielectric stack engineering. By combining IGI and gate dielectric stack engineering, high-performance depletion-free poly-Si gate high-k transistors are possible.
Keywords
Fermi level; MOSFET; aluminium compounds; elemental semiconductors; silicon; AlO; B-doped gate; Fermi pinning effect; Hf-based stacked gate dielectrics; IGI transistors; P-doped gate; Si; depletion-free CMOSFET; gate depletion; gate dielectric stack engineering; high-k CMOSFET; inverted gate implantation; poly-Si gate CMOSFET; sub-threshold characteristic; surface channel; thin AlO insertion; threshold voltage; transconductance characteristic; Annealing; CMOSFETs; High K dielectric materials; High-K gate dielectrics; Lead compounds; MOS devices; MOSFETs; Threshold voltage; Transconductance; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN
0-7803-8684-1
Type
conf
DOI
10.1109/IEDM.2004.1419306
Filename
1419306
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