A single-channel ROM-based complex digital filter implementation in the quadratic residue number systems

The implementation of complex digital filters using the quadratic residue number system (QRNs) and modified quadratic residue number system (MQRNS) is considered. These QRNS/MQRNS-based filter architectures are memory-intensive because the lookup-table approach has been used in the filter implementation. If the required number of lookup tables is reduced to a reasonable extent, single-chip VLSI implementation of such architectures may become practically feasible. A dual-clock computational module has been proposed to reduce the number of memory requirements in the QRNS/MQRNS-based complex digital filters. A direct FIR (finite-impulse response) filter architecture has been implemented using the proposed computational module in the QRNS and MQRNS schemes