Evolution of functional correlation as an engineering directive for VLSI yield enhancement

The functional yield of a double-level metal CMOS process for fabrication of 5-V VLSI 10K-gate arrays was evaluated with large-area drop-in test structures designed to identify process yield loss mechanisms. The test structure yields were correlated to device functional yields. This analysis was able to quantitatively determine the yield limiting parameters by order of significance. Pareto problem ranking analysis provides specific directions to allocate engineering resources in yield enhancement efforts without first performing extensive failure analysis or experiments, or using intuitive rationale. This method shortens the evaluation cycle for identifying specific problems and solutions by using the product itself to uncover subtle yield relationships in an ongoing manner. This gives a clear direction for yield enhancement. After evaluation of several test parameters, using various yield models, it was determined that the Stapper model provided the best mathematical fit for comparing parametric to functional yields