Second generation ORCA architecture utilizing 0.5 μm process enhances the speed and usable gate capacity of FPGAs

Author

Britton, Barry K. ; Oh, Yaw T. ; Oswald, William ; Nguyen, Ho T. ; Singh, Satwant ; Lee, Chong ; Leung, Wai-Bor ; Spivak, Carolyn ; Steward, Jim ; Chen, C.T.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

474

Lastpage

478

Abstract

This paper describes the second generation Optimized Reconfigurable Cell Array (ORCA) Field-Programmable Gate Arrays (FPGAs). Architectural Innovations combined with advanced 0.5 m process technology result in a family of high capacity and high speed FPGAs. New types of routing resources are included on the FPGA to ensure routing completion. The first ORCA part in the 2C series, the ATT2C15, contains approximately 2.5 million FETs and has a typical logic capability of about 15,000 usable gates. Preliminary benchmark results confirm the speed and logic capacity of the new parts

Keywords

CMOS logic circuits; VLSI; application specific integrated circuits; field programmable gate arrays; integrated circuit layout; network routing; 0.5 micron; 2C series; ASIC; ATT2C15; FPGA; field-programmable gate arrays; high capacity devices; high speed devices; optimized reconfigurable cell array; process technology; routing resources; second generation ORCA architecture; CMOS logic circuits; CMOS process; FETs; Field programmable gate arrays; Logic devices; Mathematical model; Programmable control; Programmable logic arrays; Reconfigurable logic; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404516

Filename

404516