A control-theoretic ABR explicit rate algorithm for ATM switches with per-VC queueing

There have been numerous studies on congestion control for the ABR service in ATM networks. These studies typically focus on the performance and fairness of the algorithms and make simplistic assumptions regarding the switch architecture and the link scheduling. One central issue of these studies has been the computation of the fair share of the link bandwidth. On the other hand, newer generation of ATM chipsets and switches now implement per-VC queueing and scheduling that is capable of providing flow isolation as well as fair sharing of the link bandwidth among contending connections. As a result, ABR congestion control algorithms can now focus on solving the congestion control problem without unnecessarily being burdened by fairness considerations. In this paper, we take advantage of the per-VC queueing/scheduling capability of the new generation of ATM switches and develop an ABR rate-based congestion control algorithm. In contrast to most algorithms that appeared in the literature which are heuristics-based, this algorithm extends previous work (see IEEE/ACM Trans. on Networking, vol.1, no.6, p.693-707, 1993) using a control-theoretic approach and takes advantage of the per-VC queue length information to achieve a simple to implement and yet complete control of the stability, rate of convergence, and performance of ABR service. Simulation results confirm the excellent performance and fairness characteristics achieved by the algorithm