SESSION 38: CMOS and interconnect reliability ESD, soft errors and backend reliability issues for nanoscale CMOS technologies

Summary form only given, as follows. This session covers cutting-edge advances in electrostatic discharge and latchup reliability issues, radiation induced soft-errors, and critical backend reliability issues including electromigration in advanced Cu/Low-k interconnects as well as backend dielectric reliability. The session starts with an excellent overview paper by C. Duvvury and G. Boselli of Texas Instruments, on ESD and latchup reliability issues for nanometer scale CMOS technologies. The second paper by M-D Ker and S-F. Hsu from the National Chia-Tung University, Taiwan discusses the issue of transient-induced latchup problems arising due to system-level ESD testing. The third paper by Y. Tosaka, et al., from Osaka University, presents a detailed and insightful study of soft-error rates in advanced CMOS circuits. The fourth paper, also on soft-errors, will be presented by Y. Kawakami, et A, from NEC Corporation, and will discuss advanced issues in SRAM SER including multi-bit upsets using accelerated testing and computational modeling. Papers five through seven are focused on backend reliability issues. The fifth paper by D. Ryuzaki et al.,f rom Hitachi Ltd., investigates the mechanism of time-dependent dielectric-constant increase in porous organosilicate glass (0%) with implications for both interconnect performance and dielectric reliability. The sixth paper by A. Isobayashi, ef d.,fr om Sony Corporation, illustrates the suitability of Cu-Ag alloy as the interconnect material for sub-45 nm technologies. The session closes with a paper by K-W. Lee, et al., from the Samsung Electronics Co., reporting on the engineering of the dielectric capping layer for improving electromigration performance in CuLow-k structure.