A VLSI architecture for real-time image convolution with large symmetric kernels

Author

Demassieux, N. ; Bernard, M. ; Joanblanq, C.

Author_Institution

ENST, Paris

fYear

1988

fDate

11-14 Apr 1988

Firstpage

1961

Abstract

The authors propose VLSI architectures for real-time convolution of an image by any large kernel with symmetries. Consideration is limited to horizontal, vertical, and central symmetries in order to reduce the hardware requirements. Based on these architectures, a chip is proposed which would implement a real-time convolution of 512×512 images with kernels up to 11×11 and allow online processing of video format images

Keywords

VLSI; computerised picture processing; online operation; real-time systems; video signals; VLSI architectures; central symmetries; chip; horizontal symmetry; large symmetric kernels; online processing; real-time image convolution; vertical symmetry; video format images; Application specific integrated circuits; Clocks; Convolution; Costs; Hardware; Image processing; Image recognition; Kernel; Pixel; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Conference_Location

New York, NY

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1988.197008

Filename

197008

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3004963