DocumentCode
3004964
Title
Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation
Author
Kawakami, Yukiya ; Hane, Masami ; Nakamura, Hideyuki ; Yamada, Takashi ; Kumagai, Kouichi
Author_Institution
Syst. Devices Res. Labs., NEC Corp., Kanagawa, Japan
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
945
Lastpage
948
Abstract
We investigated the SRAM soft error rate (SER) by using neutron irradiation testing and computational modeling. Experimentally observed multibit-error patterns can be clarified by our detailed SRAM upset model derived from the 3D device-circuit mixed-mode simulation. This work describes several essential key issues for predicting SER accounting for practical SRAM circuit-layout design issues.
Keywords
integrated circuit design; integrated circuit testing; integrated memory circuits; random-access storage; 3D mixed mode device simulation; SRAM; circuit layout design; computational modeling; multibit error patterns; multibit upsets; neutron irradiation testing; soft error rate; Circuit simulation; Computational modeling; Electronic equipment testing; Error analysis; MOS devices; MOSFETs; Neutrons; Random access memory; Semiconductor device modeling; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN
0-7803-8684-1
Type
conf
DOI
10.1109/IEDM.2004.1419340
Filename
1419340
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