On the use of modulo arithmetic comb filters in sigma delta modulators

A novel architecture of one-stage comb decimation filters for sigma-delta modulators is described. It performs the decimation of a 1-bit oversampled modulator output to an arbitrary lower output frequency. The use of modulo arithmetic throughout the filter together with the proposed algorithmic decomposition allows a low-power and area-efficient implementation. This also avoids the storing of the coefficients in a ROM or the generation of the coefficients with rather complicated up/down counters. The architecture is applicable to all comb decimation filters with sinc^k (f) response. A filter with k=3 and a programmable decimation factors has been integrated in a 3-μm CMOS process