Title :
A floating point DSP with optimizing C compiler
Author :
Boddie, J.R. ; Garen, C.J. ; Fuccio, M.L. ; Tow, J.
Author_Institution :
AT&T Bell Lab., Holmdel, NJ, USA
Abstract :
A digital signal processor (the DSP32C) has been developed which performs 32-bit floating-point operations at a rate of 25 MFLOPs and can be programmed using a standard C compiler. The authors present an overview of the architecture and instruction set with emphasis on the enhancements over its predecessor, the DSP32. The performance is expressed with common signal processor benchmarks. An application development environment is described which highlights the C compiler and hardware development system. An application example illustrates the power and ease-of-use of this DSP
Keywords :
C language; computerised signal processing; instruction sets; program compilers; 25 MFLOPS; 32 bit; C compiler; DSP32; DSP32C; application development environment; architecture; digital signal processor; floating point DSP; hardware development system; instruction set; Arithmetic; CMOS technology; Digital signal processing; Digital signal processors; Optimizing compilers; Program processors; Random access memory; Read-write memory; Signal processing; Standards development;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on
Conference_Location :
New York, NY
DOI :
10.1109/ICASSP.1988.197021
