Title :
Design of a processor bus interface ASIC for the stream memory controller
Author :
McGee, Sean W. ; Klenke, Robert H. ; Aylor, James H. ; Schwab, Andrew J.
Author_Institution :
Ross Technol. Inc., Austin, TX, USA
Abstract :
The Stream Memory Controller (SMC) is an experimental memory interface which allows hardware-assisted memory access reordering for vector computations in order to maximize the efficiency of the system memory bus. This paper describes the design and test strategies for the SMC Processor Bus Interface (PBI) and FIFO logic ASIC. This IC is designed as part of a daughter card attachment to a 40 MHz Intel i860 system. The entire integrated circuit design was completed in a top-down design environment using VHDL for synthesis and a target process of 0.75 μm. The design includes SRAM elements, combinatorial logic, and state machine components. This ASIC is the first in a series of ICs intended as a proof-of-concept of the SMC based system
Keywords :
VLSI; application specific integrated circuits; circuit CAD; computer interfaces; design for testability; integrated circuit design; integrated circuit testing; logic CAD; peripheral interfaces; storage management; storage management chips; 0.75 micron; 40 MHz; CAD; FIFO logic ASIC; Intel i860 system attachment; SRAM elements; VHDL; combinatorial logic; hardware-assisted memory access reordering; integrated circuit design; memory interface; processor bus interface ASIC; state machine components; stream memory controller; test strategies; top-down design environment; vector computations; Application specific integrated circuits; Circuit testing; Computer interfaces; Control systems; Integrated circuit synthesis; Logic design; Logic testing; Process design; Random access memory; Sliding mode control;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404519
