Title :
Squaring the FIFO in GasP
Author_Institution :
Sun Microsyst. Labs., Palo Alto, CA, USA
Abstract :
This paper presents a method for designing a special type of asynchronous circuits, called GasP circuits, and illustrates the method by a novel design of a low-latency, high-throughput FIFO, called a square FIFO. The design method includes a graphical notation that permits the specification not only of circuit topology but also of the time separation between any two succeeding events. A square FIFO test chip has been fabricated in a 0.35 μm CMOS process through MOSIS. Test results show that the square FIFO chip can sustain a maximum throughput of 1.56 giga data items per second for a large range of occupancies
Keywords :
CMOS logic circuits; asynchronous circuits; delays; integrated circuit design; logic design; 0.35 micron; CMOS process; GasP circuits; MOSIS; asynchronous circuit design; circuit topology specification; design method; graphical notation; high-throughput FIFO; low-latency FIFO; square FIFO; Application specific processors; Automata; CMOS process; Circuit testing; Delay effects; Design methodology; Laboratories; Latches; Sun; Throughput;
Conference_Titel :
Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-7695-1034-5
DOI :
10.1109/ASYNC.2001.914083
