Title :
Testing asynchronous circuits: help is on the way!
Abstract :
Summary form only given. The author describes the synergies in test problems with synchronous designs that will help in the testing of asynchronous designs. In particular, he touches upon the ATE architectures and points out where the current architectures are inadequate in supporting the testing of asynchronous circuits. The author then describes the current and planned features in ATEs that will be helpful in testing asynchronous circuits. Other topics covered include: Design for Testability (DFT); test generation; test translation; and test time management, where the development in synchronous circuit domain can be used as platform to build similar capabilities for asynchronous circuits
Keywords :
asynchronous circuits; automatic test equipment; automatic testing; design for testability; integrated circuit testing; integrated logic circuits; logic testing; ATE architectures; DFT; asynchronous circuit testing; asynchronous designs; design for testability; test generation; test time management; test translation; Asynchronous circuits; Asynchronous communication; Automatic testing; Circuit testing; Integrated circuit testing; Laboratories; Packaging machines; Semiconductor device packaging; System-on-a-chip; Test equipment;
Conference_Titel :
Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-7695-1034-5
DOI :
10.1109/ASYNC.2001.914085