A comparison of a two layer metal system built with selective CVD W plugs and elevated temperature, sputtered Al(Cu)

Summary form only given. Advanced ULSI circuits require minimum features ⩽1.0 μm to maximize packing density. In addition, metal line pinches must be ~2.0 μm and vias ⩽1.0 μm with straight walls. Thicker interlevel dielectrics for capacitance reduction mean that the aspect ratio (height/width) of vias must be ~1.0. These high aspect ratios greatly reduce the step coverage of sputtered metal causing two potential problems: (1) increased via resistance and (2) sources of reliability failure. To study these issues, the authors used a double-level metal vehicle with a range of metal 1 pitch of 1.75-3.0 μm, a metal 2 pitch range of 3.0-4.5 μm, and a range of via sizes from (0.75 μm)² to (1.5 μm)². The via chains using W to achieve an ~100% via fill had excellent results. All chains were continuous and the average resistance/via was 0.33, 0.19 and 0.13 Ω for the (0.75 μm)², (1.0 μm)², and (1.25 μm)² via chains, respectively. The standard deviation across a wafer in each case was less than 2%. When the Wfills were 75% on the smallest vias the step coverage from 325°C sputtered AlCu was poor; causing some opens and an increase in the mean and standard deviation of the Ω/via. On larger vias with same percent fill, the chains were continuous, but the resistance was greater than for the 100% fills. This is an issue when the vias have different depths due to underlying topography