Process technology - advances in source drain engineering [Session 42]

Summary form only given, as follows. This session explores recent advances in the growth and processing of source/drain contact regions. In the first paper FEOL parameters including gate leakage and VT roll-off have been investigated using strained Si/SiGe substrates. Optimization of several process parameters is necessary to reduce both parasitic gate and junction leakage. The second paper describes a strained source/drain process that uses cyclic selective epitaxial growth of SiGe/Si. When coupled with a disposable spacer process, the strain effect is shown to dramatically improve the drive current. In the following paper the impact of the etch depth of recessed SiCe on stress is measured by micro-Raman. The impact of the etch depth on performance and leakage are explored. In the fourth paper the thermally induced leakage of shallow junctions with Nisi contacts is reduced by up to 6 orders of magnitude through the incorporation of a pre-salicide fluorine implant. Finally in the last paper atomic layer deposition is used to form SiBN low k gate spacers. This dielectric results in a dramatic reduction in floating-gate interference of 90nm NAND devices