DSP chips and total processing load of FFT analysis

The paper presents a 128 bit DSP chip architecture which allows a triadic instruction set for minimizing code expansion, with 32 bit opcode and 32 bit addresses. In this instruction set the MAC instruction which takes two operands multiplies and accumulates in a destination address, the GOTO instruction which shifts left the contents of the three addresses, the IF-THEN-ELSE instruction which compares two operands and goes to the third address upon satisfaction and the ROUND instruction which converts floating point to integer are emulated and their timings found to be: MAC, 30 microseconds, GOTO, 20 microseconds, lF-THEN-ELSE, 20 microseconds and ROUND, 24 microseconds. The processing load involved in using the chip for real-time FFT is discussed