Design Consideration of High Power Density Inverter with Low-on-voltage SiC-JBS and High-speed Gate Driving of Si-IGBT

Author

Takao, K. ; Ota, C. ; Nishio, J. ; Shinohe, T. ; Ohashi, H.

Author_Institution

Corporate R&D Center, Toshiba Corp., Kawasaki

fYear

2009

fDate

15-19 Feb. 2009

Firstpage

397

Lastpage

400

Abstract

Design consideration of a three-phase inverter with 1200 V Si-IGBT and SiC-JBS hybrid pairs has been implemented to further reduce the power loss and increase the power density. A low-on-voltage SiC-JBS has been developed to reduce the conduction loss. In order to minimize the switching loss of Si-IGBT, a high-speed gate driving technique is introduced. A 4 kVA class three-phase hybrid pair inverter is fabricated to demonstrate the improvements in the power loss and efficiency. The power density of the hybrid pair inverter is estimated based on the power loss data.

Keywords

Schottky diodes; driver circuits; insulated gate bipolar transistors; power convertors; silicon compounds; wide band gap semiconductors; Si-IGBT; SiC; apparent power 4 kVA; high power density inverter; high-speed gate driving; hybrid pair inverter; junction barrier Schottky diode; low-on-voltage SiC-JBS; switching loss; three-phase inverter; voltage 1200 V; Cooling; Copper; Pulse width modulation inverters; Schottky barriers; Schottky diodes; Switching frequency; Switching loss; Temperature; Titanium; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual IEEE

Conference_Location

Washington, DC

ISSN

1048-2334

Print_ISBN

978-1-4244-2811-3

Electronic_ISBN

1048-2334

Type

conf

DOI

10.1109/APEC.2009.4802688

Filename

4802688