Highly controllable cyclic selective epitaxial growth (CySEG) for 65nm CMOS technology and beyond

A new novel raised source/drain (RSD) process by using cyclic selective epitaxial growth (CySEG) has been firstly proposed to enhance device performance for 65nm CMOSFETs and beyond. CySEG is effective in reducing the gate poly depletion effect by elevating only the source/drain region without the growth on top of the poly gate. The CySEG process is effectively combined with disposable spacer integration in order to reduce the SEG thermal budget for CMOS scaling. The disposable spacer process with CySEG dramatically enhance the drive current by 23% for pFET and restore the degraded current performance for nFET. The current performance of nFET was further improved by the RSD structure with channel width decrease. The RSD effect on releasing the compressive stress induced by shallow trench isolation (STI) might describe the opposite current performance tendency of scaled nFET.