DocumentCode
3005900
Title
Low power Gb/s CMOS interfaces
Author
Ohtomo, Y. ; Nogawa, M.
Author_Institution
NTT LSI Labs., Kanagawa, Japan
fYear
1995
fDate
8-10 June 1995
Firstpage
29
Lastpage
30
Abstract
For high-speed digital systems, it is important to develop point-to-point Gb/s interfaces that consume low power during low-transition-rate operation. This paper presents two novel Gb/s CMOS interfaces. One uses an active-pull-up (APU) technique to raise the maximum transmission speed. In the other interface, the transmission wave form is changed from digital to impulse to markedly reduce power consumption at low transition rate.
Keywords
CMOS digital integrated circuits; 1 Gbit/s; active-pull-up technique; data transmission; high-speed digital systems; impulse wave form; low power Gb/s CMOS interfaces; point-to-point interfaces; transition rate; Capacitance; Delay effects; Digital systems; Energy consumption; Feedback circuits; Hysteresis; Laboratories; Large scale integration; Signal synthesis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520673
Filename
520673
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