DocumentCode
3006114
Title
Four channel DS1 framer
Author
Parrella, Eugene L. ; Chang, Sin-Min
Author_Institution
TranSwitch Corp., Shelton, CT, USA
fYear
1994
fDate
19-23 Sep 1994
Firstpage
445
Lastpage
448
Abstract
A four channel DS1 framer chip has been developed for deployment in multichannel T1 systems, SONET add-drop multiplexers, T3 multiplexes, and ATM over T1 applications. Area reduction was realized through the use of a high speed clock, permitting use of shared resources and construction of simple arbiters for single port RAM. For further gate reduction, a state-machine based framing algorithm utilizing RAM as next state memory was developed
Keywords
SONET; application specific integrated circuits; asynchronous transfer mode; digital signal processing chips; multiplexing equipment; synchronisation; ATM over T1 applications; SONET add-drop multiplexers; T3 multiplexes; arbiters; chip area reduction; four channel DS1 framer chip; gate reduction; high speed clock; multichannel T1 systems; next state memory; shared resources; single port RAM; state-machine based framing algorithm; Add-drop multiplexers; Application specific integrated circuits; Asynchronous transfer mode; Buffer storage; Clocks; Costs; Jitter; Read-write memory; SONET; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-2020-4
Type
conf
DOI
10.1109/ASIC.1994.404523
Filename
404523
Link To Document