Hardware efficient design for narrow band power line communication modem

A hardware efficient modem design for narrow band power line communication is presented. The design adopts a 2-level modulation scheme consisting of an M-ary Bi-Orthogonal Keying (MBOK) modulation for Direct-Sequence Spread Spectrum (DSSS) scheme and a FSK modulation for chip signals. The combined DSSS and FSK modulation scheme provide a robust solution to combat severe noise effects in power line network. Another advantage of such modulation scheme is that it does not require any A/D or D/A converters and simple FFs are used for data capturing. An over-sampling technique is employed to enhance the synchronization. The baseband processing is also free of multiplication and equalization. The proposed modem uses a bandwidth of 400 kHz and can support a data rate up to 100 kbps. For AWGN channel, the BER can be lower than 10^-4 when the SNR value reaches 4dB. The FPGA implementation shows a low complexity baseband kernel consuming less than 6,000 logic gates. A chip design containing a micro-processor and the PLC modem in TSMC 0.18 μm technology is also developed.