A 10-Gb/s 0.18-μm CMOS optical receiver front-end amplifier

A 10-Gb/s integrated optical receiver front-end amplifier (FEA) that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) has been designed based on a 0.18-μm CMOS technology. A regulated-cascode (RGC) structure was used in the design of transimpedance amplifier (TIA), which overcomes the inadequate bandwidth problem caused by the large parasitic capacitance effect of the photodiode and CMOS transistors. By employing the interleaving active feedback, the bandwidth of the limiting amplifier (LA) was enhanced. And the noise analysis and optimization was especially performed to drive the FEA to obtain good noise performance. The schematic simulation results indicate that, with a photodiode parasitic capacitance of 500 fF and the bonding pad parasitic capacitance of 200 fF between which a 2-mm bond wire is inserted at the input node, the FEA provides a conversion gain of up to 90.3 dBΩ and -3-dB bandwidth of 10.38 GHz. By properly adopting the proposed noise optimization methods, the optimized average equivalent input noise current is about 2.8 μA_rms. Operating under a 1.8-V supply, the power dissipation is about 94 mW.