DocumentCode
3006510
Title
Design of an efficient dynamic time warping LSI
Author
Suzuki, Yoshitake
Author_Institution
NTT Electrical Communications Laboratories, Kanagawa, Japan
Volume
11
fYear
1986
fDate
31503
Firstpage
373
Lastpage
376
Abstract
An LSI design for use in speech recognition system is described. The Staggered Array Dynamic Programming (SADP) method[1] has been adopted as a high-speed Dynamic Time Warping (DTW) technique. A new LSI architecture has been designed for SADP. The main features of this architecture are look-up tables for address calculation and parallel processing structure for SADP calculation. The SADP-LSI is designed using a commercially available gate-array. Memories and some control logic components are attached externally. Under microprocessor control, this LSI can perform matching with about 100 reference patterns. It can also be applied to connected word recognition systems.
Keywords
Computer architecture; Digital signal processing; Dynamic programming; Equations; Laboratories; Large scale integration; Logic; Parallel processing; Pattern matching; Speech recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
Type
conf
DOI
10.1109/ICASSP.1986.1169070
Filename
1169070
Link To Document