Design of a Length-Variable FFT Processor

In this paper, design of a length variable FFT processor is presented. Mixed radix algorithm is adopted which mixes radix-2, radix-2² and radix-2/4/8 algorithms to handle 2ⁿ point, 4ⁿ point and 8ⁿ point FFT, and SDF architecture is used. By connecting or bypassing specific processing elements, the processor can be configured as 8192 point, 4096 point, 2048 point and 1024 point FFT processor. To improve processor performance, internal data is formatted as self-defined floating point, and the arithmetic for the self defined floating point is simple. The experiment results show that the self-defined floating point approach can achieve high and constant SNR. The processor is implemented on FPGA.