A novel current-mode ultra low power analog CMOS four quadrant multiplier

Author

Al-Absi, Munir Ahmad ; Hussein, Alaa ; Atti, Muhammad Taher Abuelma

Author_Institution

Electr. Eng. Dept., King Fahd Univ., Dhahran, Saudi Arabia

fYear

2012

fDate

3-5 July 2012

Firstpage

13

Lastpage

17

Abstract

A novel CMOS current mode analog multiplier is presented. The design is based on using MOSFET operating in subthreshold region to achieve ultra low power dissipation. The circuit is operated from ± 0.75V DC supply. The proposed circuit has been simulated using Tanner in 0.35μm TSMC CMOS process. Simulation results show that the total power dissipation is 2.3μW, total harmonic distortion is 0.7%, maximum linearity error is 0.3% and the bandwidth is 2.8MHz.

Keywords

CMOS analogue integrated circuits; DC supply; MOSFET; MOSFET operating; TSMC CMOS process; bandwidth 2.8 MHz; current-mode ultra low power analog cmos four quadrant multiplier; maximum linearity error; subthreshold region; total harmonic distortion; total power dissipation; ultra low power dissipation; Bandwidth; CMOS integrated circuits; Educational institutions; Power dissipation; Signal processing; Simulation; Transistors; Translinear principle; current mode; four quadrant analog multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Communication Engineering (ICCCE), 2012 International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4673-0478-8

Type

conf

DOI

10.1109/ICCCE.2012.6271143

Filename

6271143