DocumentCode :
3007037
Title :
Higher radix sparse-2 adders with improved grouping technique
Author :
Kumar, V. Chetan ; Phaneendra, P. Sai ; Ahmed, S. Ershad ; Sreehari, V. ; Muthukrishnan, N.M. ; Srinivas, M.B.
Author_Institution :
Birla Inst. of Technol. & Sci., Hyderabad, India
fYear :
2011
fDate :
21-24 Nov. 2011
Firstpage :
676
Lastpage :
679
Abstract :
When high speed addition is required for arithmetic circuits, either prefix or sparse-tree adder methodology is preferred, depending on the design constraints. Higher radix prefix adders have less logic depth but increased wiring and logic cells, whereas sparse adders have less wiring tracks, but increased logic depth. This paper presents a hybrid grouping technique for radix-4 sparse-2 adders which results in reduced wiring when compared to the existing radix-4 sparse-2 design while maintaining the advantage of both prefix and sparse techniques. Simulation results show that there is a reduction in power-delay product in radix-4 sparse-2 implementation with the proposed modification when compared to the existing implementations.
Keywords :
adders; digital arithmetic; trees (mathematics); arithmetic circuits; design constraints; grouping technique; power-delay product; prefix adder methodology; radix-4 sparse-2 adders; sparse-tree adder methodology; Adders; Bismuth; CMOS integrated circuits; Radio access networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2011 - 2011 IEEE Region 10 Conference
Conference_Location :
Bali
ISSN :
2159-3442
Print_ISBN :
978-1-4577-0256-3
Type :
conf
DOI :
10.1109/TENCON.2011.6129193
Filename :
6129193
Link To Document :
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